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Accelor unveils blockchain hardware accelerator to integrate security and performance

Accelor unveils blockchain hardware accelerator to integrate security and performance

Accelor, the first hardware accelerator bridging the blockchain and cloud industries, today emerged from stealth to unveil its Field Programmable Gate Array (FPGA) frameworks to optimize computing performance and decentralized security.

Realizing that software patching and updates have a limited capacity to fundamentally solve Blockchain’s “impossible triangle,” Accelor’s first two products, Accelor Performance Engine (APE) and Accelor Security Architecture (ASA), furnish the underlying hardware to effectively overcome these tradeoffs between security, performance, and decentralization.

Headquartered in Silicon Valley, California, Accelor is founded by a stellar team of hardware engineers who have spent more than two decades developing semiconductors for industry heavyweights Qualcomm, Nvidia and AMD. The company is backed by $2M in seed funding from Chengwei Capital, a $3B evergreen investment fund. Under development for more than a year, Accelor has performed successful live testing, and holds one approved US patent, five patent-pending, and six more ready to be filed.

“Blockchain has introduced valuable new techniques for how we share and secure private data, but the industry’s software has run up against an impossible triangle between decentralization, security, and performance. Blockchain applications currently operate on top of retrofitted legacy hardware that relies on a ‘security by patch’ process and is unsuited to the rigorous computation demanded by decentralized protocols. Commodity CPUs are not friendly to the cryptographic, network, and database operations necessary for these systems to scale without sacrificing security and it is paramount for the industry to move these intensive computing functions onto dedicated hardware. We are excited to release a crucial part of the data center infrastructure that will help Blockchain deliver on its enormous potential.”

GJ Chu, Co-founder, Accelor

Accelor Performance Engine (APE), overcomes barriers to scalability by providing dedicated hardware infrastructure to optimize the computation of intensive cryptography, storage of distributed ledger data, and transaction relays over networks. APE has been tested using Hyperledger Fabric in a live real-world environment to sustain 10x greater end-to-end throughput against software-only implementations, and has a theoretical limit upwards of 200,000 TPS.

Accelor Security Architecture (ASA) removes the most harmful threats endemic to CPU-based networking. These threats, known as Spectre, Meltdown, and Foreshadow, have been reported as critical in all the latest Trusted Execution Environments (TEE) of commercial processors, and enable malicious actors to read the most sensitive information, such as private cryptographic keys, which is detrimental to the development of blockchains and secure cloud computing environments. ASA leverages an FPGA-based confidential computing model that gives users ultimate authority over their hardware, affording each individual the flexibility to choose where to place their root of trust, thereby achieving a more decentralized hardware solution.

“While speculators have loudly focussed on blockchain’s volatile boom and bust cycles according to its market buy/sell prices, Accelor’s team is looking forward with a deeper understanding of the necessary requirements and corresponding changes that blockchain and cryptographic messaging presents for the future of network data management. Accelor’s FPGAs are a technical testament to the soundness of their technological vision, and of the team’s proven ability to address the gaps plaguing the blockchain industry’s adoption and growth.”

Pei Kang, Managing Director, Chengwei Capital, lead investor of Accelor

When running blockchain applications through CPUs, the processors in charge of managing not only our personal computers but network servers as well, the CPU is forced to juggle more than it is designed to handle which presents a tradeoff between security and performance. Accelor’s philosophy addresses this underlying problem by pioneering hardware architecture that caters to blockchain’s specific computing paradigm, tailored to fit each protocol’s unique requirements.

“Accelor’s confidential computing architecture has three key advantages to deliver a higher standard in trusted computing. Clients have more freedom to manage their devices, such as setting up their own identity management systems to authenticate each device under their control. FPGAs are faster and have greater power efficiency than general purpose processors for computationally intensive tasks such as expensive zero-knowledge proof related operations. Lastly, FPGAs are already widely used in the IoT and embedded systems market.”

Dr. Larry Shi, Associate Professor of Computer Science, Head of the Blockchain Research Team at at University of Houston (UH), and Senior Member of the Institute of Electrical and Electronics Engineers (IEEE)

Accelor’s FPGA will furnish a full suite of techniques to optimize performance throughput, privacy preservation, database management, network latency and smart-contract execution, removing roadblocks currently holding back Blockchain as a Service (BaaS) providers that service the DApps being developed in the industry. The rollout of Accelor’s performance and security optimized architectures for blockchain networking are initial products that set in motion the company’s larger vision to address the spectrum of operations required by decentralized protocols.

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